Tsunami Simulation on FPGA and its Analysis Based on Statistical Model Checking  (PDF)

Masahiro Fujita, University of Tokyo

2/27/2012, 2:00PM, GHC-6501


 In the first part of the talk, techniques by which Tsunami simulation can be accelerated with FPGA and GPU are presented. Both approaches have realized similar speed up of around 30 times over single core processors. They are based on stream based processing and the original C programs have been transformed to work with streams which are sequences of values of variables for partial differential equations at each time step. In FPGA based acceleration, streams are constructed for each variable among different time steps, whereas in GPU implementation, steams are constructed for each time step among variables for different geographical locations. These difference come from the different memory architectures used in FPGA and GPU.

In the second part of the talk, by utilizing FPGA/GPU based acceleration Tsunami simulation, various bounded properties on the accuracy of Tsunami predictions based on Tsunami simulations are statistically model checked. The statistical model checker is the one being developed by Ed Clarke's group at CMU, and our Tsunami simulation results are analyzed. Finally we will discuss about FPGA based implementation on bounded model checking for Tsunami simulations results for further speed up.


Masahiro Fujita received his Ph.D. from the University of Tokyo in 1985. He is a professor in VLSI Design and Education Center (VDEC) at the University of Tokyo. Prior to joining the University of Tokyo in 2000, he was director of CAD for VLSI in Fujitsu Laboratories of America for 6 years. He has done innovative works in the areas of digital design verification, synthesis, and testing. He has co-authored 7 books, and has over 100 publications. He has been given several research awards from Japanese scientific societies. His current research interests include synthesis and verification in higher level design stages, hardware/software co-designs and also digital/analog co-designs.


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nsfSupported by an Expeditions in Computing award from the National Science Foundation